NeoLogic, an innovative startup based in Israel, has successfully raised $10 million in Series A funding to transform the design of central processing units (CPUs) with a new technology called CMOS+. This funding will accelerate the company’s efforts to reduce energy consumption in computing, particularly for artificial intelligence (AI) data center workloads.
Founded in 2021, NeoLogic is taking a unique approach by focusing on reducing circuit complexity rather than following the traditional semiconductor industry’s path of transistor scaling. The company aims to introduce its first processors in 2026, which are expected to leverage CMOS+ technology to achieve significant energy efficiency improvements.
Innovative Circuit Design Reduces Energy Consumption
The innovative CMOS+ design combines standard complementary metal-oxide-semiconductor (CMOS) gates with reduced complexity gates. This integration enables the handling of between 6 and 32 inputs per gate, compared to the conventional limit of four inputs. As a result, NeoLogic claims that its technology can reduce transistor counts by up to three times at any process node, leading to lower power use and reduced die sizes.
According to NeoLogic, devices built with CMOS+ can achieve up to 50 percent lower energy consumption and a 40 percent reduction in chip area while maintaining latency comparable to current designs. This advancement is particularly significant, as conventional CMOS designs often require complex tree structures to manage higher input counts, which increases both the area and power requirements of the chip.
Cost Efficiency and Compatibility with Existing Processes
Another advantage of the CMOS+ technology is its compatibility with existing CMOS manufacturing processes, spanning from 130nm down to 2nm. This means that semiconductor manufacturers can adopt the new technology without needing to overhaul their current infrastructure. By minimizing die size and improving yield, CMOS+ offers cost benefits at advanced nodes where wafer costs and development expenses are typically high.
Beyond just gate improvements, CMOS+ also integrates power-efficient registers, buffers, and arithmetic blocks. Together, these elements provide chip designers with a streamlined infrastructure that simplifies processor design while enhancing power and area tradeoffs.
Talia Rafaeli, Partner at KOMPAS VC, which led the funding round, expressed confidence in NeoLogic’s potential, stating, “We are backing NeoLogic as they push the boundaries of computing with their breakthrough approach to energy-efficient processors. The team’s deep technical expertise and innovative CMOS+ technology position them to impact the AI data center space significantly.”
As NeoLogic prepares for deployment in data centers starting in 2026, it is focused on demonstrating its first processors to potential customers. The company believes that CMOS+ technology will pave the way for more efficient computing solutions without necessitating a departure from established design tools and processes.
With the backing of investors and a clear vision for the future, NeoLogic is poised to make a significant mark in the semiconductor industry, addressing the growing demand for energy-efficient computing solutions in an increasingly data-driven world.
